OpenLogics/MewtocolNet
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188 Commits 4 Branches 22 Tags
d6c00097bcba8dc9977ce57de4992e6f927171da
Commit Graph

7 Commits

Author SHA1 Message Date
Felix Weiß
d6c00097bc Simplify registers 
- add array conversion
- fixed dt area merging
 2023-07-17 00:41:27 +02:00
Felix Weiß
82821e773d Change register list source 
- add poller levels
- add new register builder pattern
 2023-07-12 18:54:07 +02:00
Felix Weiß
6c7e91f648 Add underlying byte data for registers 
- change backend logic for register r/w
- remade interface builder pattern for better syntactic sugar
- refined tests
 2023-07-12 00:32:56 +02:00
Felix Weiß
88cdc1a36c Merge PlcSeriesType into PlcType by using 16 bits 2023-07-07 17:59:22 +02:00
Felix Weiß
ab7f5ca302 Added new PLC types and auto documentation 2023-07-06 00:14:40 +02:00
Felix Weiß
f338acfe8a Fixes 2023-07-03 01:25:29 +02:00
Felix Weiß
8c2ba1f68f Added serial port support 
- complete restructure of codebase
 2023-06-30 18:39:19 +02:00